1. Field of the Invention
The present invention generally relates to a method for forming a shallow trench isolation region and, more particularly, to a method for forming a shallow trench isolation region by a nitride liner pull back process.
2. Description of the Related Art
During fabrication of integrated circuits devices are formed on a silicon substrate. The devices must be electrically isolated to ensure that each device can be operated without interfering with adjacent devices. However, as the demands for smaller circuits with higher device density increase, the isolation regions between the devices must shrink in size. Smaller isolation regions, however, can be difficult to manufacture.
Conventionally, when manufacturing devices comprising dimensions of 350 nm or larger, a process known as local oxidation of silicon (LOCOS) is used to form isolation regions between the devices. However, a phenomenon known as bird's beak phenomenon that can result from a conventional LOCOS method will introduce current leakage between devices. Further, isolation regions manufactured by a conventional LOCOS method suffer uneven surfaces.
Shallow trench isolation (STI) was developed to address the limitations of the LOCOS method in manufacturing of devices with dimensions of 250 nm or smaller. A conventional shallow trench isolation process is described in conjunction with FIG. 1A to FIG. 1D. First, a pad oxide layer 102 and a silicon nitride layer 104 are sequentially formed on a substrate 100, as shown in FIG. 1A. Next, a trench 106 is first defined using conventional lithography techniques and then etched using conventional etching techniques to form a trench 106, as shown in FIG. 1B. In FIG. 1C, an oxide liner 108 is grown within trench 106 and then the trench 106 is filled with a dielectric material. Chemical mechanical polishing (CMP) is then performed using the silicon nitride layer 104 as a polish stop layer to remove the dielectric material deposited outside the trench 106, forming a dielectric layer 110. As shown in FIG. 1D, the silicon nitride layer 104 and pad oxide layer 102 are removed to form a shallow trench isolation structure 116.
Using the shallow trench isolation process described in FIG. 1A to FIG. 1D can provide better device isolation for devices comprising smaller dimensions; however, problems can still exist. For example, mismatch between the oxide liner 108 and the substrate 100 can occur as well as dislocation between oxide liner 108 and substrate 110.
FIG. 2A to FIG. 2B disclose a process for forming an alternative STI structure the first, an oxide liner 208 is formed inside the trench 206; however, a nitride liner 210 is also formed on the oxide liner 208 to solve the problem of mismatch between the oxide liner 208 and the substrate 200 as well as to help prevent dislocation. However, in the subsequent processing steps e.g., forming a gate oxide on a surface 212, the presence of nitride liner 210 can impede reactants, such as oxygen, and results in a thinning of the gate oxide formed near the STI structure. Consequently, to address the oxide thinning issue, an additional photo mask is needed and the lithography and etch techniques must be discreetly controlled to partially remove the nitride liner 210 to form the structure shown in FIG. 2B. However, since the nitride liner 210 is quite thin, it is difficult to accurately control the lithography and etch techniques and the process window is therefore very small.
Moreover, in conventional lithography techniques, a tradeoff between high resolution (R) and sufficient depth of focus (DOF) exists. Theoretically, light with a short wavelength and a larger numerical aperture (NA) is used to ensure that the resolution (R) obtained from the lithography technique is optimum. However, use of such light requires high cost exposure equipment. Further, high-throughput equipment for producing and using such light is often not available in the market. The large NA suffers from small DOF, and results in difficulties controlling the process. Therefore, as a result of the tradeoffs required, the structure in FIG. 2B manufactured by a conventional technique often suffers inconsistent device quality.
U.S. Pat. No. 6,180,493 describes another method for forming a shallow trench isolation region that attempts to resolve the above-mentioned problems. The method essentially discloses forming a shallow trench isolation region in a substantially oxygen-filled atmosphere, in which the shallow trench isolation region includes a plurality of insulating layers inside the trench. However, this method not only requires forming a plurality of insulating layers, buffer layers, and oxide liners, it also needs to control the thickness of these layers by tuning process parameters. Thus, this method is complicated, which can increase costs and reduce throughput.
Accordingly, there is a need for an improved method of forming a shallow trench isolation region that is not only cost effective, but also resolves the problem of dislocation and oxide thinning.